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XMEGA A [MANUAL]
8077I–AVR–11/2012
18.3.10 PER1 – Period register 1
18.3.11 PER2 – Period register 2
18.3.12 PER3 – Period register 3
18.3.13 COMP0 – Compare register 0
The COMP0, COMP1, COMP2, and COMP3 registers represents the 32-bit value, COMP. COMP is constantly
compared with the counter value (CNT). A compare match will set COMPIF in the INTFLAGS register, and an interrupt is
generated if it is enabled. COMPIF will be set on next count after a match.
If the COMP value is higher than the PER value, no RTC compare match interrupt requests or events will be generated.
After writing the high byte of the COMP register, the write condition for setting OVFIF and COMPIF, as well as the
overflow and compare match wake-up condition, will be disabled for the following two RTC32 clock cycles.
18.3.14 COMP1 – Compare register 1
Bit
7
6
5
4
3
2
1
0
+0x09
PER[15:8]
Read/Write
R/W
Reset Value
0
Bit
7
6
5
432
1
0
+0x0A
PER[23:16]
Read/Write
R/W
Reset Value
0
000
0
Bit
7
6
5
432
1
0
+0x0B
PER[31:24]
Read/Write
R/W
Initial Value
0
Bit
7
6
5
4
3
2
1
0
+0x0C
COMP[7:0]
Read/Write
R/W
Initial Value
0
Bit
7
6
5
4
3
2
1
0
+0x0D
COMP[15:8]
Read/Write
R/W
Initial Value
0